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Job Code	BE1462
Department	BE
Discipline	Electronics Engineering
Description	The candidate will develop electronic boards for the new CERN-wide General Machine Timing (GMT) system. This system provides fine synchronization to all of CERN facilities, including all accelerators and many experimental areas. It does so using a dedicated timing network with one master and many hundreds of receivers. In the frame of the injectors renovation project, many of the electronic boards in the GMT will have to be designed, manufactured, tested and installed.
Special Requirements	University degree in Electronics Engineering or similar. Analogue and digital (HDL) design experience. English or French.
Training Value	The candidate will gain experience in cutting edge design technologies for networking systems, including fine synchronization techniques such as Phase Locked Loops, spectral purity measurements and cabling delay compensation. In addition there will be exposure to all other electronics projects in the section, which span all types of applications of hardware for accelerators.
Supervisor	JAVIER SERRANO

Job Code	PH118
Department	PH
Discipline	Electronics Engineering
Description	Description (Control Module) ATLAS is the only detector in the world where persons will go inside during shutdown periods. During the maintenance periods it is expected that up to 150 people could be present in the cavern at the same time, most of them working inside the intricacies of the detector and completely hidden and invisible from outside. In case of emergency, it could be extremely difficult and dangerously long for a rescue team to locate every person who could be in danger. Under these circumstances, a granular system for finding persons is then mandatory. The system must cope with the harsh environment and must be totally passive (no badges or other active equipment should be worn) to avoid voluntary or casual deactivation. FPIAA (Finding Persons Inside ATLAS Areas)is based on a large number (at the present about 400) of PIR (Passive InfraRed) sensors, each one detecting the presence of a person in a relatively small volume (~ 30 m3) and distributed to cover the most critical locations in the cavern. The goal of this job is to acquire all sensor data from a CAN fieldbus timestamp it and stored in a real time database which should be kept alive for years without interruption. The FPIAA application would access to this data and generate the necessary alarms, but the system should be built in such a way that even if FPIAA software crashes, the data acquisition and storing would never be interrupted. To understand the goals of ATLAS experiment see http://atlas.ch/movie/index.html.
Special Requirements	Also Electrotechnical, Computer Science Engineering, or Phisicist with similar experience Special Requirements Basic knowledge CAN fieldbus, OPC server and clients, realtime databases, supervision systems like PVSS.
Training Value	The applicants will work in a very competitive, international and of the most advanced computing environments and use state of the art technology.
Supervisor	GIANPAOLO BENINCASA

Job Code	PH127
Department	PH
Discipline	Electronics Engineering
Description	The Tile Calorimeter is a sub-system of the ATLAS experiment, one of the experiments of the LHC collider. The Tile calorimeter is built in three cylindrical sections, two 3 m long sections and one 6 m long section. Each cylinder is built by joining 64 modules. Most of the front end electronics is installed in drawers in the outer part of the modules, and is controlled remotely mainly using CANbus protocol and a SCADA distributed system running in several PCs. The context of the job offer is to be integrated in the team in charge of the control of systems such as low voltage power supplies, high voltage power supplies, cooling, etc, and keeping these controls integrated in the global control system of the ATLAS experiment and always operational. The data collected by the control system is recorded in Oracle databases and needs to be analyzed in depth to understand the way each equipment operates. At the same time, a surface lab equipped with part of the systems that are running in the detector in the cavern is being developed, to be used for prototyping, repairs and studies of the systems that are in operation at the detector. For such a task, commercial tools as well as tools developed at CERN are used. By being involved in this project, it is possible to get an overall view of the execution of an electronics control and monitoring project. Last "state of art" resources will be applied for these tasks. The candidate will take part in the analysis of the data collected by the monitoring system and will interact with the physicist teams that will be running the detector and will have to coordinate actions with them.
Special Requirements	Degree in Electronics or Software Engineering
Training Value	To get skills on concurrent engineering
Supervisor	ANA MARIA HENRIQUES CORREIA

Job Code	PH1623
Department	PH
Discipline	Electronics Engineering
Description	Design of communications integrated circuits The candidate will work at CERN in the micro-electronics section for a period of two years. He/she will be involved in the development of a high speed data communications ASIC that will be used in the future SLHC experiments. The engineer will use a mix of full-custom and standard cell design techniques and will be involved on the design of variety of circuits such as phase-locked loops, serializers, clock recover circuits, high speed line drivers and on the design of digital logic. Additionally, the engineer will be also involved on evaluation testing of the ASIC.
Special Requirements	A university degree in electronics engineering is required. The candidate should have understanding of analogue electronics and communication circuits. The candidate should be acquainted with the use of CAD tools for full-custom ASIC design. Knowledge of Verilog or VHDL hardware programming languages would be considered as an asset.
Training Value	The candidate will be integrated in an electronics engineering group for which the main activity is ASIC design. The candidate will develop skills on the design of analogue and communications circuit, will become proficient on the use of full-custom and standard cell design CAD tools and will learn and use equipment for ASIC characterization and evaluation testing.
Supervisor	PAULO RODRIGUES SIMOES MOREIRA

Job Code	PH2602
Department	PH
Discipline	Electronics Engineering
Description	The Tile Calorimeter is a sub-system of the ATLAS experiment, one of the experiments that operate at the CERN LHC collider. The Tile calorimeter is built in three cylindrical sections, two 3 m long sections and one 6 m long section. Each cylinder is built by joining 64 modules. Most of the front end electronics is installed in drawers in the outer part of the modules, and is controlled and monitored remotely mainly using CANbus protocol and a SCADA distributed system running in several PCs. The context of the job offer is to be integrated in the team in charge of the control of systems such as low voltage power supplies, high voltage power supplies, cooling, etc, and keeping these controls integrated in the global control system of the ATLAS experiment and always operational. The data collected by the control system is recorded in Oracle databases and needs to be analysed in depth to understand the way each equipment operates. At the same time, a surface lab equipped with part of the systems that are running in the detector in the cavern is operational and is used for prototyping, repairs and studies of the systems that are in operation at the detector. For such a task, commercial tools as well as tools developed at CERN are used. By being involved in this project, it is possible to get an overall view of the execution of an electronics control and monitoring project. Last "state of art" resources will be applied for these tasks. The candidate will take part in the analysis of the data collected by the monitoring system and will interact with the physicist teams that will be running the detector and will have to coordinate actions with them.
Special Requirements	Electronics engineering, software or physics engineering
Training Value	Gain experience in control systems, electronics and software
Supervisor	ANA MARIA HENRIQUES CORREIA

Job Code	PH2762
Department	PH
Discipline	Electronics Engineering
Description	ATLAS Insertable B-Layer : Module and System tests for state-of-art pixel modules In the frame work of the international collaboration between CERN and scientific worldwide institutes, the new Inserted B-Layer (IBL) project represents the first upgrade phase of the present LHC Atlas Pixel Detector, to be completed by 2014. The integration of the IBL detector system comprises the final assembly of the detector on the surface of ATLAS as well as the electrical integration of the IBL detector to the off-detector readout, supply and control system. Each stage, from modules to staves to the final assembled detector, includes a suitable set of electrical performance tests to validate the functionality of the IBL modules (connectivity, readout, noise) with the newly designed powering and readout system for the detector (system test). The goal of this system test is to validate the design of the off-detector electronics (readout, power) with modules and stave of the new pixel detector. The aim of the final integration tests is to operate and study the completed IBL detector under realistic operation. It will allow the study of coherent effects (e.g. cross talk,¿) between the modules and staves, as well as a comparison of module performance in the final detector to module production data. As the last tests before the installation, the tests will provide a final and definitive QA of the assembled detector prior to transport to the ATLAS experiment.
Special Requirements	The functions include: · Definition of electrical and electronics tests on pixel modules and their power and readout system. · Performance validation of prototypes for detector readout and powering components · Definition and implementation of procedures for system tests and pixel stave tests · Tests and optimization of pixel modules and staves with measurements the detector performance parameters (noise, calibration, testbeam) · Analysis and interpretation of test data
Training Value	The ATLAS Insertable B-Layer project will provide training to young engineers in an international multi-discipinary reseach and development environment. The engineers will receive training in state-of-the-art semiconductor sensor and the tests of costume VLSI electronics for the readout of pixel sensors. The candidate will be trained in all aspects of system integration and quality-assurance protocols of high-reliability pixel detector modules.
Supervisor	HEINZ PERNEGGER

Job Code	PH2822
Department	PH
Discipline	Electronics Engineering
Description	Tilecal is the central hadronic calorimeter of the ATLAS experiment for the LHC. The Trigger and Data Acquisition software used in its operation is common to all ATLAS. On top of it, the Tilecal online software is used to control and monitor the specific detector electronics. The front-end electronics which are located in the outer most part of the detector, sample and digitize the signals from approximately 10000 channels at a rate of 40 MHz. The trigger signals gathered from the calorimeters and the muon chambers are processed by the Central Trigger Processor and provide a maximum Level 1 trigger rate of 100 kHz to the different detectors which are then responsible for the read-out of the events from the event pipelines. The Read-Out Drivers (ROD) in the back-end electronics are responsible for the reconstruction of the energy and time of the signals deposited in each read-out channel, and transmit the data to the Read-Out Buffers of the Level 2 trigger. The back-end electronics also host the infrastructure for the monitoring of the detector, where dedicated tasks perform quality checks on the data sampled at a Level 1 rate and on the data sampled after the Level 2 trigger decision. During the current operation for a period of 18 to 24 months, the luminosity is expected to gradually increase the Level 1 trigger rate up to 75 % of its nominal value. This initiates a process of fine tunning of the Tilecal online software, where the main goal is to achieve the maximum data taking efficiency, as it is a key point to the scientific success of the experiment. The candidate will participate in the optimization of the reconstruction algorithm in the RODs and improvement of the sampling rate of the monitoring tasks in order to assess the quality of the data.
Special Requirements	Degree in engineering with interest in data acquisition in high energy physics
Training Value	Gain experience in practical aspects of data acquisition in high energy physics
Supervisor	CARLOS ANTONIO SOLANS SANCHEZ

Job Code	PH2842
Department	PH
Discipline	Electronics Engineering
Description	To participate in the development of custom DC-DC converters for Trackers at the Super LHC. The front-end DCDC converters need to be optimized for minimum noise emission and size, and they need to be tolerant to intense magnetic fields and to high levels of radiation. Prototypes of these converters have been produced: they need to be characterized and tested with front-end systems. The compatibility between the converters and the systems needs to be studied.
Special Requirements	Design of power electronics. Remote control of instruments. Computing for data analysis.
Training Value	The project will bring the trainee in the field of electromagnetic compatibility of front-end electronics for particle detectors, which is of primary importance for the SLHC experiments. Also, the tests of DCDCs offers the possibility to learn the design and operation of different types of front-end electronics systems. The work will be performed in close collaboration with the radiation tolerant power ASICs designers at CERN.
Supervisor	GEORGES BLANCHOT

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